CS3600 — Homework 1

How to submit

chmod g+r ~/cs3600/1/hw_1.txt

Questions

1. A special type of address register required by a system that implements user visible stack ___________.
2. Interrupts are provided primarily as a way to improve processor utilization. (True/False)
3. It is not possible for a communications interrupt to occur while a printer interrupt is being processed.(True/False)
4. The __________ contains the data to be written into memory and receives the data read from memory.
   A) I/O address register

   B) memory address register

   C) I/O buffer register

   D) memory buffer register
5. The four main structural elements of a computer system are:
   A) Processor, Main Memory, I/O Modules and System Bus

   B) Processor, I/O Modules, System Bus and Secondary Memory

   C) Processor, Registers, Main Memory and System Bus

   D) Processor, Registers, I/O Modules and Main Memory
6. The operating system acts as an interface between the computer hardware and the human user.(True/False)
7. The interrupt can occur at any time and therefore at any point in the execution of a user program.(True/False)
8. The fetched instruction is loaded into the Program Counter. (True/False)
9. External, nonvolatile memory is also referred to as __________ or auxiliary memory.
10. Digital Signal Processors deal with streaming signals such as audio and video. (True/False)
11. When an external device becomes ready to be serviced by the processor the device sends a(n) ___________ signal to the processor.
    A) access

    B) halt

    C) handler

    D) interrupt
12. A system bus transfers data between the computer and its external environment. (True/False)
13. The processor controls the operation of the computer and performs its data processing functions.(True/False)
14. The fetched instruction is loaded into the __________ .
15. When a new block of data is read into the cache the __________ determines which cache location the block will occupy.
16. Registers that are used by system programs to minimize main memory references by optimizing register use are called ___________.
17. The __________ holds the address of the next instruction to be fetched.
    A) Accumulator (AC)

    B) Instruction Register (IR)

    C) Instruction Counter (IC)

    D) Program Counter (PC)
18. The ___________ routine determines the nature of the interrupt and performs whatever actions are needed.
    A) interrupt handler

    B) instruction signal

    C) program handler

    D) interrupt signal
19. The processing required for a single instruction is called a(n) __________ cycle.
20. Each location in Main Memory contains a _________ value that can be interpreted as either an instruction or data.
21. One mechanism Intel uses to make its caches more effective is __________ , in which the hardware examines memory access patterns and attempts to fill the caches speculatively with data that is likely to be requested soon.
    A) mapping

    B) handling

    C) interconnecting

    D) prefetching
22. The unit of data exchanged between cache and main memory is __________ .
    A) block size

    B) map size

    C) cache size

    D) slot size
23. The __________ is a point-to-point link electrical interconnect specification that enables high-speed communications among connected processor chips.
    A) QPI

    B) DDR3

    C) LRUA

    D) ISR
24. In a two-level memory hierarchy the Hit Ratio is defined as the fraction of all memory access found in the slower memory.(True/False)
25. When an external device is ready to accept more data from the processor, the I/O module for that external device sends an ___________ signal to the processor.